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Field plate optimization in low-power high-gain source-gated transistors

机译:低功率高增益源栅晶体管的场板优化

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摘要

Source-gated transistors (SGTs) have potentially very high output impedance and low saturation voltages, which make them ideal as building blocks for high performance analog circuits fabricated in thin-film technologies. The quality of the saturation is greatly influenced by the design of the field-relief structure incorporated into the source electrode. Starting from measurements on self-aligned polysilicon structures, we show through numerical simulations how the field plate design can be improved. A simple source field plate around 1µm long situated several tens of nm above the semiconductor can increase the low-voltage intrinsic gain by more than two orders of magnitude and offers adequate tolerance to process variations in a moderately scaled thin-film SGT.
机译:源极门控晶体管(SGT)可能具有非常高的输出阻抗和低饱和电压,这使其非常适合用作薄膜技术制造的高性能模拟电路的构建基块。饱和的质量很大程度上受引入到源电极中的场释放结构的设计的影响。从对自对准多晶硅结构的测量开始,我们通过数值模拟显示了如何改进场板设计。一个简单的源极场板(位于半导体上方数十纳米处)长约1μm,可以将低压本征增益提高两个数量级以上,并为中等规模的薄膜SGT中的工艺变化提供足够的容差。

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